View CY7C1484V25-167AXC_2728677.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

72-mbit (2m x 36/4m x 18) pipelined dcd sync sram cy7c1484v25 cy7c1485v25 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05286 rev. *h revised april 24, 2007 features ? supports bus operation up to 250 mhz ? available speed grades are 250, 200, and 167 mhz ? registered inputs and outputs for pipelined operation ? optimal for performance (double cycle deselect) ? depth expansion without wait state ? 2.5v core power supply (v dd ) ? 2.5v/1.8v io supply (v ddq ) ? fast clock-to-output times ? 3.0 ns (for 250-mhz device) ? provide high performance 3-1-1-1 access rate ? user selectable burst counter supporting intel ? pentium ? interleaved or linear burst sequences ? separate processor and controller address strobes ? synchronous self timed writes ? asynchronous output enable ? cy7c1484v25 , cy7c1485v25 available in jedec- standard pb-free 100-pin tqfp , pb-free and non-pb-free 165-ball fbga package ? ieee 1149.1 jtag-compatible boundary scan ? ?zz? sleep mode option functional description [1] the cy7c1484v25/cy7c1485v25 sram integrates 2m x 36/4m x 18 sram cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (ce 1 ), depth-expansion chip enables (ce 2 and ce 3 ), burst control inputs (adsc , adsp , and adv ), write enables (bw x and bwe ), and global write (gw ). asynchronous inputs include the output enable (oe ) and the zz pin. addresses and chip enables are registered at the rising edge of clock when either address strobe processor (adsp ) or address strobe controller (adsc ) are active. subsequent burst addresses can be internally generated as controlled by the advance pin (adv ). address, data inputs, and write co ntrols are registered on-chip to initiate a self timed write cycle. this part supports byte write operations (see ?pin definitions? on page 5 and ?truth table? on page 8 for further details). writ e cycles can be one to four bytes wide, as controlled by the byte write control inputs. gw active low causes all bytes to be written. this device incor- porates an additional pipelined enable register, which delays turning off the output buffers an additional cycle when a deselect is executed. this feature allows depth expansion without penalizing system performance. the cy7c1484v25/cy7c1485v25 operates from a +2.5v core power supply while all outputs operate with a +2.5v or a +1.8v supply. all inputs and outputs are jedec-standard jesd8-5-compatible. selection guide 250 mhz 200 mhz 167 mhz unit maximum access time 3.0 3.0 3.4 ns maximum operating current 450 450 400 ma maximum cmos standby current 120 120 120 ma note 1. for best practices recommendations, please refer to the cypress application note an1064, sram system guidelines . [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 2 of 26 logic block diagram ? cy7c1484v25 (2m x 36) logic block diagram ? cy7c1485v25 (4m x 18) address register adv clk burst counter and logic clr q1 q0 adsp adsc mode bw d bw c bw b bw a bwe gw ce 1 ce 2 ce 3 oe dq d, dqp d byte write register dq c ,dqp c byte write register dq b ,dqp b byte write register dq a, dqp a byte write register enable register pipelined enable output registers sense amps memory array output buffers dq a, dqp a byte write driver dq b ,dqp b byte write driver dq c ,dqp c byte write driver dq d, dqp d byte write driver input registers a 0,a1,a a[1:0] sleep control zz e 2 dqs dqp a dqp b dqp c dqp d address register adv clk burst counter and logic clr q1 q0 adsc bw b bw a ce 1 dq b, dqp b byte write register dq a, dqp a byte write register enable register oe sense amps memory array adsp 2 a [1:0] mode ce 2 ce 3 gw bwe pipelined enable dq s, dqp a dqp b output registers input registers e output buffers dq b, dqp b byte write driver dq a, dqp a byte write driver sleep control zz a 0, a1, a [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 3 of 26 pin configurations 100-pin tqfp pinout a a a a a 1 a 0 a a v ss v dd a a a a a a a a dqp b dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a dqp a dqp c dq c dq c v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1484v25 (2m x 36) nc a a a a a 1 a 0 a a v ss v dd a a a a a a a a a nc nc v ddq v ssq nc dqp a dq a dq a v ssq v ddq dq a dq a v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a nc nc v ssq v ddq nc nc nc nc nc nc v ddq v ssq nc nc dq b dq b v ssq v ddq dq b dq b v dd nc v ss dq b dq b v ddq v ssq dq b dq b dqp b nc v ssq v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1485v25 (4m x 18) nc a a [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 4 of 26 pin configurations (continued) 165-ball fbga (15 x 17 x 1.4 mm) pinout cy7c1484v25 (2m x 36) cy7c1485v25 (4m x 18) 234 567 1 a b c d e f g h j k l m n p r tdo nc/288m nc/144m dqp c dq c dqp d nc dq d ce 1 bw b ce 3 bw c bwe a ce 2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d a a v ddq bw d bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq c v ss dq c v ss dq c dq c nc v ss v ss v ss v ss nc v ss a1 dq d dq d nc nc v ddq v ss tms 891011 a adv a adsc nc oe adsp a nc/576m v ss v ddq nc/1g dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a a0 a v ss a 234 567 1 a b c d e f g h j k l m n p r tdo nc/288m nc/144m nc nc dqp b nc dq b a ce 1 nc ce 3 bw b bwe a ce 2 nc dq b dq b mode nc dq b dq b nc nc nc a a v ddq nc bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd ?v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq b v ss nc v ss dq b nc nc v ss v ss v ss v ss nc v ss a1 dq b nc nc nc v ddq v ss tms 891011 a adv a adsc a oe adsp a nc/576m v ss v ddq nc/1g dqp a v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss a a a dq a nc nc zz dq a nc nc dq a a v ddq a a [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 5 of 26 pin definitions pin name io description a 0 , a 1 , a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 are sampled active. a1: a0 are fed to the two-bit counter. bw a ,bw b bw c ,bw d input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all bytes are written, regardless of the values on bw x and bwe ). bwe input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. clk input- clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low during a burst operation. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select or deselect the device. adsp is ignored if ce 1 is high. ce 1 is sampled only when a new external address is loaded. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select or deselect the device. ce 2 is sampled only when a new external address is loaded. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select or dese lect the device. ce 3 is sampled only when a new external address is loaded. oe input- asynchronous output enable, asynchronous input, active low . controls the direction of the io pins. when low, the io pins behave as outputs. w hen deasserted high, dq pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv input- synchronous advance input signal, sampled on the rising edge of clk, active low . when asserted, it automatically increments the address in a burst cycle. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a1: a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. adsc input- synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a1: a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. zz input- asynchronous zz ?sleep? input, active high . when asserted high, places the device in a non-time-critical ?sleep? condition with data integr ity preserved. for normal operat ion, this pin has to be low or left floating. zz pin has an internal pull down. dqs, dqps io- synchronous bidirectional data io lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they del iver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dqs and dqp x are placed in a tri-state condition. v dd power supply power supply inputs to the core of the device . v ss ground ground for the core of the device . v ssq [2] io ground ground for the io circuitry . v ddq io power supply power supply for the io circuitry . note 2. applicable for tqfp package. for bga package v ss serves as ground for the core and the io circuitry. [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 6 of 26 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the rising edge of the clock. the cy7c1484v25/cy7c1485v25 supports secondary cache in systems using either a linear or interleaved burst sequence. the interleaved burst order supports pentium and i486? processors. the linear burst sequence is suited for processors that use a linear burst sequence. the burst order is user selectable, and is determined by sampling the mode input. accesses can be initiated with either the adsp or adsc . the adv input controls address advancement through the burst sequence. a two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the addr ess for the rest of the burst access. byte write operations are qualif ied with the byte write enable (bwe ) and byte write select (bw x ) inputs. gw overrides all byte write inputs and writes data to all four bytes. all writes are simplified with on-chip synchronous self timed write circuitry. synchronous chip selects ce 1 , ce 2 , ce 3 and an asynchronous output enable (oe ) provide easy bank selection and output tri-state control. adsp is ignored if ce 1 is high. single read accesses this access is initiated when the following conditions are satisfied at cloc k rise: (1) adsp or adsc is asserted low, (2) chip selects are all asserted active, and (3) the write signals (gw , bwe ) are all deasserted high. adsp is ignored if ce 1 is high. the address presented to the address inputs is stored into the address adv ancement logic and the address register while being presented to the memory core. the corre- sponding data is allowed to propagate to the input of the output registers. at the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within t co if oe is active low. the only exception occurs when the sram is emerging from a deselected state to a selected state; its outputs are always tri-stated during the first cycle of the access. after th e first cycle of the access, the oe signal controls the outputs. consecutive single read cycles are supported. the cy7c1484v25/cy7c1485v25 is a double cycle deselect part. after the sram is deselected at clock rise by the chip select and either adsp or adsc signals, its output tri-states immediately after th e next clock rise. single write accesses initiated by adsp this access is initiated when both of the following conditions are satisfied at clock rise: (1) adsp is asserted low, and (2) chip select is asserted active. the address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. the write signals (gw , bwe , and bw x ) and adv inputs are ignored during th is first cycle. adsp triggered write accesses need two clock cycles to complete. if gw is asserted low on the second clock rise, the data presented to the dq x inputs is written into the corre- sponding address location in the memory core. if gw is high, then the bwe and bw x signals control the write operation. the cy7c1484v25/cy7c1485v25 provides byte write capability that is described in the ?truth table for read/write? on page 9 . asserting bwe with the selected byte write input will selectively write to only the desired bytes. bytes not selected during a byte write operation remain unaltered. a synchronous self timed write mechanism is provided to simplify the write operations. because the cy7c1484v25/cy7c1485v25 is a common io device, the output enable (oe ) must be deasserted high before presenting data to the dq inputs. doing so tri-states the output drivers. as a safety precaution, dq are automatically mode input- static selects burst order . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence . this is a strap pin and must remain static during device operation. mode pin has an internal pull up. tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. if the jtag feature is not used, this pin should be discon nected. this pin is not available on tqfp packages. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not used, this pin can be disconnected or connected to v dd . this pin is not available on tqfp packages. tms jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not used, this pin can be disconnected or connected to v dd . this pin is not available on tqfp packages. tck jtag clock clock input to th e jtag circuitry . if the jtag feature is not used , this pin must be connected to v ss . this pin is not available on tqfp packages. nc ? no connects . not internally connected to the die nc(144m, 288m, 576m, 1g) ? these pins are not connected . they will be used for expansion to the 144m, 288m, 576m and 1g densities. pin definitions (continued) pin name io description [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 7 of 26 tri-stated whenever a write cycle is detected, re gardless of the state of oe . single write accesses initiated by adsc adsc write accesses are initiated when the following condi- tions are satisfied: (1) adsc is asserted low, (2) adsp is deasserted high, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (gw , bwe , and bw x ) are asserted active to conduct a write to the desired byte(s). adsc triggered write accesses need a single clock cycle to complete. the address pr esented is loaded into the address register and the address advancement logic while being delivered to the memory core. the adv input is ignored during this cycle. if a global write is conducted, the data presented to the dq x is written into the corresponding address location in the memory core. if a byte write is conducted, only the selected bytes are written. bytes not selected during a byte write operation remain unaltered. a synchronous self-timed write mechanism is provided to simplify the write operations. because the cy7c1484v25/cy7c1485v25 is a common io device, the output enable (oe ) must be deasserted high before presenting data to the dq x inputs. doing so tri-states the output drivers. as a safety precaution, dq x are automati- cally tri-stated whenever a wr ite cycle is dete cted, regardless of the state of oe . burst sequences the cy7c1484v25/cy7c1485v25 provides a two-bit wraparound counter, fed by a [1:0] , that implements either an interleaved or linear burst sequence. the interleaved burst sequence is designed specifical ly to support intel pentium applications. the linear burst sequence is designed to support processors that follow a linear burst sequence. the burst sequence is user selectable through the mode input. both read and write burst operations are supported. asserting adv low at clock rise will automatically increment the burst counter to the next address in the burst sequence. both read and write burst operations are supported. sleep mode the zz input pin is asynchronous. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data int egrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected bef ore entering the ?sleep? mode. ce s, adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low . interleaved burst address table (mode = floating or v dd ) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min max unit i ddzz sleep mode standby current zz > v dd ? 0.2v 120 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz active to sleep current this parameter is sampled 2t cyc ns t rzzi zz inactive to exit sleep current this parameter is sampled 0 ns [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 8 of 26 truth table the truth table for cy7c1484v25/cy7c1485v25 follows. [3, 4, 5, 6, 7] operation add. used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq deselect cycle, power down none h x x l x l x x x l-h tri-state deselect cycle, power down none l l x l l x x x x l-h tri-state deselect cycle, power down none l x h l l x x x x l-h tri-state deselect cycle, power down none l l x l h l x x x l-h tri-state deselect cycle, power down none l x h l h l x x x l-h tri-state sleep mode, power down none x x x h x x x x x x tri-state read cycle, begin burst external l h l l l x x x l l-h q read cycle, begin burst external l h l l l x x x h l-h tri-state write cycle, begin burst external l h l l h l x l x l-h d read cycle, begin burst external l h l l h l x h l l-h q read cycle, begin burst external l h l l h l x h h l-h tri-state read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h tri-state read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h tri-state write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cycle, suspend burst current x x x l h h h h h l-h tri-state read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h tri-state write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d notes 3. x = ?don't care.? h = logic high, l = logic low. 4. write = l when any one or more byte write enable signals and bwe = l or gw = l. write = h when all byte write enable signals, bwe , gw = h. 5. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 6. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw x . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of t he write cycle to allow the outputs to tri-state. oe is a don't care for the remainder of the write cycle. 7. oe is asynchronous and is not sampled with the clock rise. it is masked internally during writ e cycles. during a read cycle all d ata bits are tri-state when oe is inactive or when the device is deselected, and all data bits behave as output when oe is active (low). [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 9 of 26 truth table for read/write the read/write truth table for cy7c1484v25 follows. [5, 8] function (cy7c1484v25) gw bwe bw d bw c bw b bw a read hhxxxx read hlhhhh write byte a ? (dq a and dqp a ) hlhhhl write byte b ? (dq b and dqp b )hlhhlh write bytes b, a h l h h l l write byte c ? (dq c and dqp c ) hlhlhh write bytes c, a h l h l h l write bytes c, b h l h l l h write bytes c, b, a h l h l l l write byte d ? (dq d and dqp d ) hl lhhh write bytes d, a h l l h h l write bytes d, b h l l h l h write bytes d, b, a h l l h l l write bytes d, c h l l l h h write bytes d, c, a h l l l h l write bytes d, c, b hllllh write all bytes hlllll write all bytes lxxxxx truth table for read/write the read/write truth table for cy7c1485v25 follows. [5] function (cy7c1485v25) gw bwe bw b bw a read h h x x read h l h h write byte a ? (dq a and dqp a )hlhl write byte b ? (dq b and dqp b )hllh write all bytes h l l l note 8. table contains only a partial listing of the byte write combinations. any combination of bw x is valid. appropriate write is based on which byte write is active. [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 10 of 26 ieee 1149.1 serial boundary scan (jtag) the cy7c1484v25/cy7c1485v2 5 incorporates a serial boundary scan test access port (tap). this port operates in accordance with ieee standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. these functions from the i eee specification are excluded because their inclusion places an added delay in the critical speed path of the sram. note that the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec-standard 2. 5v or 1.8v i/o logic levels. the cy7c1484v25/cy7c1485v25 contains a tap controller, instruction register, boundary sc an register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tie tck low (v ss ) to prevent device clocking. tdi and tms are internally pulled up and may be unconnected. they may alternatively be connected to v dd through a pull up resistor. tdo must be left unconnected. during power up, the device comes up in a reset state, which does not interfere with the operation of the device. the 0/1 next to each state repr esents the value of tms at the rising edge of tck. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input gives commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball serially inputs information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information about loading the instruction register, see the tap controller state diagram . tdi is internally pulled up and can be uncon- nected if the tap is unused in an application. tdi is connected to the most significant bit (msb) of any register. (see tap controller block diagram .) test data-out (tdo) the tdo output ball serially clo cks data-out from the registers. whether the output is active depends on the current state of the tap state machine. the output changes on the falling edge of tck. tdo is connected to th e least significant bit (lsb) of any register. (see tap controller state diagram .) performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo balls and enable data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. tap controller state diagram test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 tap controller block diagram bypass register 0 instruction register 0 1 2 identication register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . selection circuitry tck tms tap controller tdi tdo selection circuitry [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 11 of 26 instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the ?tap controller block diagram? on page 10 . during power up, the instruction register is loaded with the idcode instru ction. it is also loaded with the idcode instruction if the controller is placed in a reset state, as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to enable fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the x36 configuration has a 73-bit-long register and the x1 8 configuration has a 54-bit-long register. the boundary scan register is lo aded with the contents of the ram io ring when the tap co ntroller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the io ring. the boundary scan order tables on page 14 show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction regi ster. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in ?identification register defini- tions? on page 13 . tap instruction set overview eight different instructions are possible with the three-bit instruction register. all combinations are listed in ?identification codes? on page 14 . three of these instructions are listed as reserved and must not be used. the other five instructions are described in this section in detail. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. the tap controller cannot be used to load address data or control signals into the sram and cannot preload the io buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather, it performs a capture of the io ring when these instructions are executed. instructions are loaded into the tap controller during the shift- ir state when the instruction register is placed between tdi and tdo. during this state, inst ructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction once it is shifted in, the tap controller must be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction, which is to be executed whenever the instructi on register is loaded with all zeros. extest is not implemented in this sram tap controller, and therefore this device is not compliant to 1149.1. the tap controller does recognize an all-zero instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. there is one difference between the two instructions. un like the sample/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and enables the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register at power up or whenever the tap controller is in a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo balls when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 m andatory instruction. the preload portion of this instru ction is not implemented, so the device tap controller is not fully 1149.1 compliant. when the sample/preload instruction is loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. be aware that the tap controller clock can only operate at a frequency up to 10 mhz, but the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output may undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this does not harm the device, but there is no guarantee as to the value that may be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller?s capture setup plus hold time (t cs plus t ch ). [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 12 of 26 the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if th is is an issue, it is still possible to capture all other signals and simply ignore the value of the clk captured in the boundary scan register. after the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo balls. note that because the preload part of the command is not implemented, putting the tap to the update-dr state while performing a sample/preload instruction has the same effect as the pause-dr command. bypass when the bypass instruction is loaded in t he instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo balls. the advantage of the bypass instructio n is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions. tap timing tap ac switching characteristics over the operating range [9, 10] parameter description min max unit clock t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high time 20 ns t tl tck clock low time 20 ns output times t tdov tck clock low to tdo valid 10 ns t tdox tck clock low to tdo invalid 0 ns setup times t tmss tms setup to tck clock rise 5 ns t tdis tdi setup to tck clock rise 5 ns t cs capture setup to tck rise 5 hold times t tmsh tms hold after tck clock rise 5 ns t tdih tdi hold after clock rise 5 ns t ch capture hold after clock rise 5 ns t tl test clock (tck) 123456 test mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov dont care undefined notes 9. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 10. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns. [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 13 of 26 2.5v tap ac test conditions input pulse levels .................................................v ss to 2.5v input rise and fall time........... .......................................... 1 ns input timing referenc e levels .........................................1.25v output reference levels.................................................1.25v test load termination supply vo ltage.............................1.25v 1.8v tap ac test conditions input pulse levels.............. ....................... 0.2v to v ddq ? 0.2 input rise and fall time .....................................................1 ns input timing reference levels...... ....................................... .9v output reference levels ............. ..................................... 0.9v test load termination supply vo ltage .............................. 0.9v 2.5v tap ac output load equivalent tdo 1.25v 20pf z = 50 ? o 50 ? 1.8v tap ac output load equivalent tdo 0.9v 20pf z = 50 ? o 50 ? tap dc electrical characteristics and operating conditions (0c < t a < +70c; v dd = 2.5v 0.125v unless otherwise noted) [11] parameter description test conditions min. max. unit v oh1 output high voltage i oh = ?1.0 ma v ddq = 2.5v 1.7 v v oh2 output high voltage i oh = ?100 av ddq = 2.5v 2.1 v v ddq = 1.8v 1.6 v v ol1 output low voltage i ol = 1.0 ma v ddq = 2.5v 0.4 v v ol2 output low voltage i ol = 100 av ddq = 2.5v 0.2 v v ddq = 1.8v 0.2 v v ih input high voltage v ddq = 2.5v 1.7 v dd + 0.3 v v ddq = 1.8v 1.26 v dd + 0.3 v v il input low voltage v ddq = 2.5v ?0.3 0.7 v v ddq = 1.8v ?0.3 0.36 v i x input load current gnd v i v ddq ?5 5 a identification register definitions instruction field cy7c1484v25 (2m x 36) cy7c1485v25 (4m x 18) description revision number (31:29) 000 000 describes the version number device depth (28:24) 01011 01011 reserved for internal use architecture/memory type(23:18) 000110 0001 10 defines memory type and architecture bus width/density (17:12) 100100 010100 defines width and density cypress jedec id code (11:1) 00000110100 0000011010 0 enables unique identification of sram vendor id register presence indicator (0) 1 1 ind icates the presence of an id register note 11. all voltages refer to v ss (gnd). [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 14 of 26 scan register sizes register name bit size (x36) bit size(x18) instruction 3 3 bypass 1 1 id 32 32 boundary scan order -165bga 73 54 identification codes instruction code description extest 000 captures io ring contents. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affe ct sram operations. sample z 010 captures io ring contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/ preload 100 captures io ring contents. places the boundary scan register between tdi and tdo. does not affect sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations. boundary scan exit order (2m x 36) bit # 165-ball id bit # 165-ball id bit # 165-ball id bit # 165-ball id 1 c1 21 r3 41 l10 61 b8 2d1 22 p2 42k11 62 a7 3e1 23 r4 43j11 63 b7 4d2 24 p6 44k10 64 b6 5 e2 25 r6 45 j10 65 a6 6f1 26 n6 46h11 66 b5 7g1 27p11 47g11 67 a5 8f2 28 r8 48f11 68 a4 9g2 29 p3 49e11 69 b4 10 j1 30 p4 50 d10 70 b3 11 k1 31 p8 51 d11 71 a3 12 l1 32 p9 52 c11 72 a2 13 j2 33 p10 53 g10 73 b2 14 m1 34 r9 54 f10 15 n1 35 r10 55 e10 16 k2 36 r11 56 a10 17 l2 37 n11 57 b10 18 m2 38 m11 58 a9 19 r1 39 l11 59 b9 20 r2 40 m10 60 a8 [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 15 of 26 boundary scan exit order (4m x 18) bit # 165-ball id bit # 165-ball id bit # 165-ball id 1d2 19r8 37 c11 2e2 20p3 38 a11 3f2 21p4 39 a10 4g2 22p8 40 b10 5j1 23p9 41 a9 6 k1 24 p10 42 b9 7l1 25r9 43 a8 8m1 26r10 44 b8 9n1 27r11 45 a7 10 r1 28 m10 46 b7 11 r2 29 l10 47 b6 12 r3 30 k10 48 a6 13 p2 31 j10 49 b5 14 r4 32 h11 50 a4 15 p6 33 g11 51 b3 16 r6 34 f11 52 a3 17 n6 35 e11 53 a2 18 p11 36 d11 54 b2 [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 16 of 26 maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v dd relative to gnd........ ?0.5v to +3.6v supply voltage on v ddq relative to gnd ...... ?0.5v to +v dd dc voltage applied to outputs in tri-state........................................... ?0.5v to v ddq + 0.5v dc input voltage ................................... ?0.5v to v dd + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... ........... ............ ........... >2001v (mil-std-883, method 3015) latch up current .................................................... >200 ma operating range range ambient temperature v dd v ddq commercial 0c to +70c 2.5v ?5%/+5% 1.7v to v dd industrial ?40c to +85c electrical characteristics over the operating range [12, 13] parameter description test conditions min. max. unit v dd power supply voltage 2.375 2.625 v v ddq io supply voltage for 2.5v io 2.375 v dd v for 1.8v io 1.7 1.9 v v oh output high voltage for 2.5v io, i oh = ?1.0 ma 2.0 v for 1.8v io, i oh = ?100 a1.6v v ol output low voltage for 2.5v io, i ol = 1.0 ma 0.4 v for 1.8v io, i ol = 100 a0.2v v ih input high voltage [12] for 2.5v io 1.7 v dd + 0.3v v for 1.8v io 1.26 v dd + 0.3v v v il input low voltage [12] for 2.5v io ?0.3 0.7 v for 1.8v io ?0.3 0.36 v i x input leakage current except zz and mode gnd v i v ddq ?5 5 a input current of mode input = v ss ?30 a input = v dd 5 a input current of zz input = v ss ?5 a input = v dd 30 a i oz output leakage current gnd v i v ddq, output disabled ?5 5 a i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 4.0-ns cycle, 250 mhz 450 ma 5.0-ns cycle, 200 mhz 450 ma 6.0-ns cycle, 167 mhz 400 ma i sb1 automatic ce power down current?ttl inputs v dd = max, device deselected, v in v ih or v in v il f = f max = 1/t cyc 4.0-ns cycle, 250 mhz 200 ma 5.0-ns cycle, 200 mhz 200 ma 6.0-ns cycle, 167 mhz 200 ma i sb2 automatic ce power down current?cmos inputs v dd = max, device deselected, v in 0.3v or v in > v ddq ? 0.3v, f = 0 all speeds 120 ma i sb3 automatic ce power down current?cmos inputs v dd = max, device deselected, or v in 0.3v or v in > v ddq ? 0.3v f = f max = 1/t cyc 4.0-ns cycle, 250 mhz 200 ma 5.0-ns cycle, 200 mhz 200 ma 6.0-ns cycle, 167 mhz 200 ma i sb4 automatic ce power down current?ttl inputs v dd = max, device deselected, v in v ih or v in v il , f = 0 all speeds 135 ma notes 12. overshoot: v ih (ac) < v dd +1.5v (pulse width less than t cyc /2). undershoot: v il (ac) >?2v (pulse width less than t cyc /2). 13. power up: assumes a linear ramp from 0v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd. [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 17 of 26 capacitance tested initially and after any design or proc ess change that may affect these parameters. parameter description test conditions 100 tqfp package 165 fbga package unit c address address input capacitance t a = 25 c, f = 1 mhz, v dd = 2.5v v ddq = 2.5v 66pf c data data input capacitance 5 5 pf c ctrl control input capacitance 8 8 pf c clk clock input capacitance 6 6 pf c i/o input/output capacitance 5 5 pf thermal resistance tested initially and after any design or proc ess change that may affect these parameters. parameter description test conditions 100 tqfp package 165 fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 24.63 16.3 c/w jc thermal resistance (junction to case) 2.28 2.1 c/w ac test loads and waveforms output r = 1667 ? r = 1583 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% 1 ns 1 ns (c) output r = 14k ? r = 14 k ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 0.9v 1.8v all input pulses v ddq ? 0.2 0.2 90% 10% 90% 10% 1 ns 1 ns (c) 2.5v io test load 1.8v io test load [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 18 of 26 switching characteristics over the operating range. timing reference level is 1.25v when v ddq = 2.5v and is 0.9v when v ddq = 1.8v. test conditions shown in (a) of ?ac test loads and waveforms? on page 17 unless otherwise noted. parameter description 250 mhz 200 mhz 167 mhz unit min max min max min max t power v dd (typical) to the first access [14] 111 ms clock t cyc clock cycle time 4.0 5 6 ns t ch clock high 2.0 2.0 2.2 ns t cl clock low 2.0 2.0 2.2 ns output times t co data output valid after clk rise 3.0 3.0 3.4 ns t doh data output hold after clk rise 1.3 1.3 1.5 ns t clz clock to low-z [15, 16, 17] 1.3 1.3 1.5 ns t chz clock to high-z [15, 16, 17] 3.0 3.0 3.4 ns t oev oe low to output valid 3.0 3.0 3.4 ns t oelz oe low to output low-z [15, 16, 17] 000 ns t oehz oe high to output high-z [15, 16, 17] 3.0 3.0 3.4 ns setup times t as address setup before clk rise 1.4 1.4 1.5 ns t ads adsc , adsp setup before clk rise 1.4 1.4 1.5 ns t advs adv setup before clk rise 1.4 1.4 1.5 ns t wes gw , bwe , bw x setup before clk rise 1.4 1.4 1.5 ns t ds data input setup before clk rise 1.4 1.4 1.5 ns t ces chip enable setup before clk rise 1.4 1.4 1.5 ns hold times t ah address hold after clk rise 0.4 0.4 0.5 ns t adh adsp , adsc hold after clk rise 0.4 0.4 0.5 ns t advh adv hold after clk rise 0.4 0.4 0.5 ns t weh gw , bwe , bw x hold after clk rise 0.4 0.4 0.5 ns t dh data input hold after clk rise 0.4 0.4 0.5 ns t ceh chip enable hold after clk rise 0.4 0.4 0.5 ns notes 14. this part has an internal voltage regulator; t power is the time that the power needs to be supplied above v dd (minimum) initially before a read or write operation can be initiated. 15. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in part (b) of ?ac test loads and waveforms? on page 17 . transition is measured 200 mv from steady-state voltage. 16. at any supplied voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not impl y a bus contention condition, bu t reflect parameters guaranteed over worst case user conditions. device is designed to achieve high-z before low-z under the same system conditions. 17. this parameter is sampled and not 100% tested. [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 19 of 26 switching waveforms figure 1 shows read cycle timing waveforms. [18] figure 1. read cycle timing t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces gw, bwe,bw data out (dq) high-z t doh t co adv t oehz t co single read burst read t oev t oelz t chz burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a3) q(a2 + 3) a2 a3 deselect cycle burst continued with new base address adv suspends burst dont care undefined x clz t note 18. on this diagram, when ce is low: ce 1 is low, ce 2 is high, and ce 3 is low. when ce is high: ce 1 is high, ce 2 is low, or ce 3 is high. [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 20 of 26 figure 2 shows write cycle timing waveforms. [18, 19] figure 2. write cycle timing switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces bwe, bw x adv burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds gw t weh t wes byte write signals are ignored for rst cycle when adsp initiates burst adsc extends burst adv suspends burst dont care undefined d(a1) high-z data in (d) data out (q) note 19. full width write can be initiated by either gw low; or by gw high, bwe low, and bw x low. [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 21 of 26 figure 3 shows read/write cycle timing waveforms. [18, 20, 21] figure 3. read/write cycle timing switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a2 t ceh t ces d ata out (q) high-z adv single write d(a3) a4 a5 a6 d(a5) d(a6) data in (d) burst read back-to-back reads high-z q(a2) q(a1) q(a4) q(a4+1) q(a4+2) t weh t wes q(a4+3) t oehz t dh t ds t oelz t clz t co back-to-back writes a1 bwe, bw x a3 dont care undefined notes 20. the data bus (q) remains in high-z following a write cycle, unless a new read access is initiated by adsp or adsc . 21. gw is high. [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 22 of 26 figure 4 shows zz mode timing waveforms. [22, 23] figure 4. zz mode timing switching waveforms (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) dont care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only notes 22. device must be deselected when entering zz mode. see ?truth table? on page 8 for all possible signal conditions to deselect the device. 23. dqs are in high-z when exiting zz sleep mode [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 23 of 26 ordering information not all of the speed, package and temperat ure ranges are available. please contact your local sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram part and package type operating range 167 CY7C1484V25-167AXC 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) pb-free commercial cy7c1485v25-167axc cy7c1484v25-167bzc 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) cy7c1485v25-167bzc cy7c1484v25-167bzxc 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1485v25-167bzxc cy7c1484v25-167axi 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) pb-free lndustrial cy7c1485v25-167axi cy7c1484v25-167bzi 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) cy7c1485v25-167bzi cy7c1484v25-167bzxi 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1485v25-167bzxi 200 cy7c1484v25-200axc 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) pb-free commercial cy7c1485v25-200axc cy7c1484v25-200bzc 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) cy7c1485v25-200bzc cy7c1484v25-200bzxc 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1485v25-200bzxc cy7c1484v25-200axi 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) pb-free lndustrial cy7c1485v25-200axi cy7c1484v25-200bzi 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) cy7c1485v25-200bzi cy7c1484v25-200bzxi 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1485v25-200bzxi 250 cy7c1484v25-250axc 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) pb-free commercial cy7c1485v25-250axc cy7c1484v25-250bzc 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) cy7c1485v25-250bzc cy7c1484v25-250bzxc 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1485v25-250bzxc cy7c1484v25-250axi 51-85050 100-pin thin quad fl at pack (14 x 20 x 1.4 mm) lead-free industrial cy7c1485v25-250axi cy7c1484v25-250bzi 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) cy7c1485v25-250bzi cy7c1484v25-250bzxi 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1485v25-250bzxi [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 24 of 26 package diagrams figure 5. 100-pin thin plastic quad fl atpack (14 x 20 x 1.4 mm), 51-85050 note: 1. jedec std ref ms-026 2. body length dimension does not include mold protrusion/end flash mold protrusion/end flash shall not exceed 0.0098 in (0.25 mm) per side 3. dimensions in millimeters body length dimensions are max plastic body size including mold mismatch 0.300.08 0.65 20.000.10 22.000.20 1.400.05 121 1.60 max. 0.05 min. 0.600.15 0 min. 0.25 0-7 (8x) stand-off r 0.08 min. typ. 0.20 max. 0.15 max. 0.20 max. r 0.08 min. 0.20 max. 14.000.10 16.000.20 0.10 see detail a detail a 1 100 30 0 5 1 3 51 80 81 gauge plane 1.00 ref. 0.20 min. seating plane 51-85050-*b [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 25 of 26 ? cypress semiconductor corporation, 2002-2007. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent o r other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. i486 is a trademark, and intel and pentium are registered tr ademarks of intel corporation. all product and company names mentioned in this document are the trademarks of their respective holders. figure 6. 165-ball fbga (15 x 17 x 1.4 mm), 51-85165 package diagrams (continued) a 1 pin 1 corner 17.000.10 15.000.10 7.00 1.00 ?0.450.05(165x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.35 1.40 max. seating plane 0.530.05 0.25 c 0.15 c pin 1 corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a c 1.00 5.00 0.36 +0.05 -0.10 51-85165-*a [+] feedback [+] feedback
cy7c1484v25 cy7c1485v25 document #: 38-05286 rev. *h page 26 of 26 document history page document title: cy7c1484v25/cy7c1485v25 72-mb it (2m x 36/4m x 18) pipelined dcd sync sram document number: 38-05286 rev. ecn no. issue date orig. of change description of change ** 114672 08/21/02 pks new data sheet *a 118285 01/20/03 hgk changed tco from 2.4 to 2.6 ns for 250 mhz updated features on package offering updated ordering information changed advanced information to preliminary *b 233368 see ecn njy changed timing diagrams changed logic block diagrams modified functional description modified ?functional overview? section added boundary scan order for all packages included thermal numbers and capacitance values for all packages included idd and isb values removed 250-mhz offering and included 225-mhz speed bin changed package outline for 165fbga package removed 119-bga package offering *c 299511 see ecn syt removed 225-mhz offering and included 250-mhz speed bin changed t cyc from 4.4 ns to 4.0 ns for 250-mhz speed bin changed ja from 16.8 to 24.63 c/w and jc from 3.3 to 2.28 c/w for 100 tqfp package on page # 16 added lead-free information for 100- pin tqfp and 165 fbga packages added comment of ?lead-free bg packa ges availability? below the ordering information *d 320197 see ecn pci changed typo in the part number from cy7c1484v33 and cy7c1485v33 to cy7c1484v25 and cy7c1485v25 respective ly on page numbers 2, 3, 4 and 21 *e 331513 see ecn pci unshaded 200 and 167 mhz speed bins in the ac/dc table and selection guide address expansion pins/balls in the pinouts for all packages are modified as per jedec standard added address expansion pins in the pin definitions table added industrial operating range modified v ol , v oh test conditions updated ordering information table *f 416221 see ecn rxu converted from preliminary to final changed address of cypress semiconduc tor corporation on page# 1 from ?3901 north first street? to ?198 champion court? changed the description of i x from input load current to input leakage current on page# 16 changed the i x current values of mode on page # 16 from -5 a and 30 a to -30 a and 5 a changed the i x current values of zz on page # 16 from -30 a and 5 a to -5 a and 30 a changed v ih < v dd to v ih < v dd on page # 16 replaced package name column with package diagram in the ordering information table *g 472335 see ecn vkn added the maximum rating for supply voltage on v ddq relative to gnd changed t th , t tl from 25 ns to 20 ns and t tdov from 5 ns to 10 ns in tap ac switching characteristics table updated the ordering information table. *h 1062042 see ecn vkn/kkvtmp add ed footnote #2 re lated to v ssq [+] feedback [+] feedback

▲Up To Search▲

Price & Availability of CY7C1484V25-167AXC

	To Download CY7C1484V25-167AXC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .